The present invention relates generally to silicon on insulator (SOI) field effect transistor structures, and more specifically to such structures formed on a conventional silicon bulk wafer.
Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semi-conductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and xe2x80x9coffxe2x80x9d state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance problem, silicon on insulator technology (SOI) has been gaining popularity. However, SOI field effect transistors suffer from floating body effects. The floating body effect occurs because the channel, or body, of the transistor is not connected to a fixed potential and, therefore the body takes on charge based on recent operation of the transistor. The floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate. This problem is particular apparent for passgate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the xe2x80x9coffxe2x80x9d position to prevent charge leakage from the storage capacitor.
Accordingly, there is a strong need in the art for a semiconductor field effect transistor structure, and a method for forming such structure, that includes the low junction capacitance and low xe2x80x9coffxe2x80x9d state leakage characteristics of the SOI FET but does not suffer the disadvantages of a floating body potential.
A first object of this invention is to provide a method of forming a field effect transistor on a semiconductor substrate which includes etching an insulating trench around the perimeter of an active region of said transistor to isolate the active region from other structures on said substrate and etching an insulating undercut in the bottom of the insulating trench to isolate at least a portion of the bottom surface of the active region from the substrate. Portions of the active region may be doped to form each of a source region and a drain region on opposing sides of a central channel region. The insulating undercut may isolate at least a portion of both the source region and the drain region from the silicon substrate. Furthermore, the insulating undercut may isolate at least a portion of the central channel region from the silicon substrate.
Etching the undercut includes: a) forming a protective layer on the side walls and bottom of the trench; b) performing a vertical anisotropic etch of said layer to remove such layer to expose silicon substrate at the bottom of the trench; and c) performing an isotropic etch of the silicon substrate to form said undercut. The isotropic etch may be performed using a KOH wet etch. The protective layer may be silicon dioxide and filling the undercut may include performing a chemical vapor deposition using at least one of SiH4 and TEOS.
A second object of this invention is to provide a field effect transistor formed on a semiconductor substrate which includes an active region, including a central channel region and a source region and a drain region disposed on opposite sides of said central channel region, a bridge region, with a cross section area smaller than a cross section of the active region, consecutively coupling the central channel region with said semiconductor substrate; and an insulator isolating said active region and said bridge region from other structures formed on said semiconductor substrate. The central channel region, the bridge region, and the semiconductor substrate may all be the same conductivity and the source region and drain region may be of an opposite conductivity. The insulator may extend under a bottom surface of the active region to at least partially isolate the source region and the drain region from the silicon substrate such that the semiconductor junctions between the source region and the silicon substrate and the drain region and the silicon substrate are at least one of reduced in size or eliminated. The insulator may be silicon dioxide.
A third object of this invention is to provide a semiconductor device including a plurality of field effect transistors formed on a semiconductor substrate, each transistor including: a) an active region, including a central channel region and a source region and a drain region each on opposing sides of the central channel region; b) a bridge region, with a cross section area smaller than a cross section of the active body region, conductively coupling the central channel region with said semiconductor substrate; and c) an insulator isolating said active body region and said bridge region from at least one other of said plurality of transistors. The central channel region, the bridge region, and the semiconductor substrate all may be the same conductivity and the source region and drain region may be of an opposite conductivity. The insulator may extend under a bottom surface of the active region to at least partially isolate the source region and the drain region from the silicon substrate such that the semiconductor junctions between the source region and the silicon substrate and the drain region and the silicon substrate are at least one of reduced in size or eliminated. The insulator isolating at least two of the plurality of transistors may be silicon dioxide.